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2013
- Robert Wille; Mathias Soeken; Christian Otterstedt; Rolf Drechsler
Improving the Mapping of Reversible Circuits to Quantum Circuits Using Multiple Target Lines . In: 18th Asia and South Pacific Design Automation Conference. Asia and South Pacific Design Automation Conference (ASP-DAC-2013), 18th, January 22-25, Yokohama, Japan, IEEE, 2013.
- Hoang M. Le; Daniel Große; Rolf Drechsler
Scalable Fault Localization for SystemC TLM Designs. In: Design, Automation & Test in Europe. Design, Automation & Test in Europe (DATE-13), March 18-22, Grenoble, France, IEEE, 2013.
- Robert Wille; Martin Gogolla; Mathias Soeken; Mirco Kuhlmann; Rolf Drechsler
Towards a Generic Verification Methodology for System Models. In: Design, Automation & Test in Europe. Design, Automation & Test in Europe (DATE-13), March 18-22, Grenoble, France, IEEE, 2013.
- Julia Seiter; Robert Wille; Mathias Soeken; Rolf Drechsler
Determining Relevant Model Elements for the Verification of UML/OCL Specifications. In: Design, Automation & Test in Europe. Design, Automation & Test in Europe (DATE-13), March 18-22, Grenoble, France, IEEE, 2013.
- Rolf Drechsler; Ian Harris; Ecker Wolfgang; Rainer Findenig; Robert Wille
Design and Verification of Embedded Systems from Natural Language Descriptions. In: Design, Automation & Test in Europe. Design, Automation & Test in Europe (DATE-13), March 18-22, Grenoble, France, IEEE, 2013.
- Rolf Drechsler; Daniel Große; Hoang M. Le; André Sülflow
Synchronized Debugging across Different Abstraction Levels in System Design. In: Embedded World Conference 2013. Embedded World Conference, February 26-28, Nuremberg, Germany, o.A. 2013.
- Mathias Soeken; Robert Wille; Eugen Kuksa; Rolf Drechsler
Generierung von OCL-Ausdrücken aus natürlichsprachlichen Beschreibungen. In: 16. ITG/GMM/GI-Workshop "Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen". ITG/GMM/GI-Workshop "Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen" (MBMV-13), 16. March 12-14, Rostock, Germany, o.A. 2013.
- Mathias Soeken; Robert Wille; Rolf Drechsler
Formale Verifikation von UML-basierten Spezifikationen - Prüfung der Korrektheit von Systementwürfen vor deren Implementierung. In: Industrie Management - Zeitschrift für industrielle Geschäftsprozesse, Vol. 01/2013, Pages 44-48, GITO, 2013.
- Robert Wille; Mathias Soeken; Nils Przigoda; Rolf Drechsler
Effect of Negative Control Lines on the Exact Synthesis of Reversible Circuits. In: Journal of Multiple-Valued Logic and Soft Computing, Vol. o.A. Page o.A. o.A. 2013.
- Elsa Andrea Kirchner; Rolf Drechsler
Towards Formalization of Embedded Brain Reading. In: Design, Automation & Test in Europe 2013. Design, Automation & Test in Europe (DATE-2013), International Workshop on Neuromorphic and Brain-Based Computing Systems, March 18-22, Grenoble, France, o.A. 3/2013.
- Laura Tague; Mathias Soeken; Shin-ichi Minato; Rolf Drechsler
Debugging of Reversible Circuits using πDDs. In: Proceedings of the 43rd International Symposium on Multiple-Valued Logic . The International Symposium on Multiple-Valued Logic (ISMVL-13), 43rd, May 22-24, Toyama, Japan, IEEE, 2013.
- Robert Wille; Hongyan Zhang; Rolf Drechsler
Fault Ordering for Automatic Test Pattern Generation of Reversible Circuits. In: Proceedings of the 43rd International Symposium on Multiple-Valued Logic . The International Symposium on Multiple-Valued Logic (ISMVL-13), 43rd, May 22-24, Toyama, Japan, IEEE, 2013.
- Nabila Abdessaied; Mathias Soeken; Robert Wille; Rolf Drechsler
Exact Template Matching Using Boolean Satisfiability. In: Proceedings of the 43rd International Symposium on Multiple-Valued Logic . The International Symposium on Multiple-Valued Logic (ISMVL-13), 43rd, May 22-24, Toyama, Japan, IEEE, 2013.
- Hoang M. Le; Daniel Große; Rolf Drechsler; Vladimir Herdt
Verifying SystemC using an Intermediate Verification Language and Symbolic Simulation. In: Design Automation Conference. Design Automation Conference (DAC-13), June 2-6, Austin, TX, United States, IEEE, 2013.
- Melanie Diepenbeck; Mathias Soeken; Daniel Große; Rolf Drechsler
Towards Automatic Scenario Generation from Coverage Information . In: 8th International Workshop on Automation of Software Test . International Workshop on Automation of Software Test (AST-13), 8th, May 18-19, San Francisco, United States, IEEE, 2013.
- Hoang m. Le; Daniel Große; Vladimir Herdt; Rolf Drechsler
SystemC Verifikation mittels symbolischer Simulation einer Zwischensprache. In: Electronic Design Automation Workshop. Electronic Design Automation Workshop (edaWorkshop-13), May 14-16, Dresden, Germany, VDE, 2013.
- Oliver Keszöcze; Mathias Soeken; Eugen Kuska; Rolf Drechsler
lips: An IDE for Model Driven Engineering based on Natural Language Processing. In: Workshop on Natural Language Analysis in Software Engineering. Workshop on Natural Language Analysis in Software Engineering (NaturaLiSE-13), May 25, San Francisco, CA, United States, o.A. 2013.
- Rolf Drechsler; Mathias Soeken
Hardware-Software Co-Visualization: Developing Systems in the Holodeck. In: IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems . IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS-13), April 8-10, Karlovy Vary, Czech Republic, IEEE, 2013.
- Nabila Abdessaied; Robert Wille; Mathias Soeken; Rolf Drechsler
Reducing the Depth of Quantum Circuits Usind Additional Lines. In: Proceedings of the 5th Conference on Reversible Computation. Conference on Reversible Computation (RC-13), 5th, July 4-5, Victoria , BC, Canada, Lecture Notes in Computer Science (LNCS), Springer, 2013.
- Arighna Deb; Debesh Kumar Das; Hafizur Rahaman; Bhargab B. Bhattacharya; Robert Wille; Rolf Drechsler
Reversible Circuit Synthesis of Symmetric Functions Using a Simple Regular Structure. In: Proceedings of the 5th Conference on Reversible Computation. Conference on Reversible Computation (RC-13), 5th, July 4-5, Victoria, BC, Canada, Lecture Notes in Computer Science (LNCS), Springer, 2013.
- Kamalika Datta; Gaurav Rathi; Robert Wille; Indranil Sengupta; Hafizur Rahaman; Rolf Drechsler
Exploiting Negative Control Lines in the Optimization of Reversible Circuits . In: Proceedings of the 5th Conference on Reversible Computation. Conference on Reversible Computation (RC-13), 5th, July 4-5, Victoria, BC, Canada, Lecture Notes in Computer Science, Springer, 2013.
- Philipp Niemann; Robert Wille; Rolf Drechsler
On the "Q" in QMDDs: Efficient Representation of Quantum Functionality in the QMDD Data-structure. In: Proceedings of the 5th Conference on Reversible Comuptation. Conference on Reversible Computation (RC-13), 5th, July 4-5, Victoria, BC, Canada, Lecture Notes in Computer Science (LNCS), Springer, 2013.
- Jannis Stoppe; Robert Wille; Rolf Drechsler
Data Extraction from SystemC Designs using Debug Symbols and the SystemC API. In: IEEE Computer Society Annual Symposium on VLSI. IEEE Computer Society Annual Symposium on VLSI (ISVLSI-13), August 5-8, Natal, Brazil, IEEE, 2013.
2012
- Stephan Eggersglüß; Rolf Drechsler
A Highly Fault-Efficient SAT-Based ATPG Flow. In: IEEE Design & Test of Computers, Vol. 29, No. 4, Pages 63-70, IEEE Press, 7/2012.
- Mathias Soeken; Robert Wille; Christoph Hilken; Nils Przigoda; Rolf Drechsler
Synthesis of Reversible Circuits with Minimal Lines for Large Functions. In: Conference Proceedings. Asia and South Pacific Design Automation Conference (ASP-DAC-12), 17th, January 30 - February 2, Sydney, New South Wales, Australia, o.A. 2012.
- Robert Wille; Mathias Soeken; Rolf Drechsler
Debugging of Inconsistent UML/OCL Models. In: Conference Proceedings. Design, Automation & Test in Europe (DATE-12), March 12-16, Dresden, Germany, o.A. 2012.
- Mathias Soeken; Robert Wille; Rolf Drechsler
Eliminating Invariants in UML/OCL Models. In: Conference Proceedings. Design, Automation & Test in Europe (DATE-12), March 12-16, Dresden, Germany, o.A. 2012.
- Finn Haedicke; Daniel Große; Rolf Drechsler
A Guiding Coverage Metric for Formal Verification. In: Conference Proceedings. Design, Automation & Test in Europe (DATE-12), March 12-16, Dresden, Germany, o.A. 2012.
- Robert Wille; Rolf Drechsler; Christof Oswald; Alberto Garcia-Ortiz
Automatic Design of Low-Power Encoders Using Reversible Circuit Synthesis. In: Conference Proceedings Design, Automation & Test in Europe. Design, Automation & Test in Europe (DATE-12), March 12-16, Dresden, Germany, o.A. 2012.
- Stephan Eggersglüß; Rene Krenz-Baath; Andreas Glowatz; Friedrich Hapke; Rolf Drechsler
A New SAT-based ATPG for Generating Highly Compacted Test Sets. In: Proceedings. IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS-12), April 18-20, IEEE-Verlag, 2012.
- Stephan Eggersglüß; Rolf Drechsler
High Quality Test Pattern Generation and Boolean Satisfiability. ISBN 978-1-4419-9975-7, Springer, 3/2012.
- Mathias Soeken; Stefan Frehse; Robert Wille; Rolf Drechsler
RevKit: An Open Source Toolkit for the Design of Reversible Circuits. In: Reversible Computation 2011, Series: Lecture Notes in Computer Science (LNCS) Reversible Computation. Workshop on Reversible Computation (RC-2011), 3rd, July 4-5, Gent, Belgium, Pages 64-76, Lecture Notes in Computer Science (LNCS), Vol. 7165, Springer, 2012.
- Rolf Drechsler; Robert Wille
Synthesis of Reversible Circuits Using Decision Diagramm. In: International Symposium on Electronic System Design . International Symposium on Electronic System Design (ISED-2012), December 19-22, Kolkata, India, o.A. 2012.
- Hoang M. Le; Daniel Große; Rolf Drechsler
From Requirements and Scenarios to ESL Design in System C. In: International Symposium on Electronic System Design . International Symposium on Electronic System Design (ISED-2012), December 19-22, Kolkata, India, o.A. 2012.
- Marcio F. S. Oliveira; Christoph Kuznik; Wolfgang Mueller; Finn Haedicke; Hoang M. Le; Daniel Große; Rolf Drechsler; Wolfgang Ecker; Volkan Esen
The System Verification Methodology for Advanced TLM Verification. In: International Conference on Hardware/Software Codesign and System Synthesis. International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS-2012), October 7-12, Tampere, Finland, ACM, 2012.
- Stefan Frehse; Görschwin Fey; Eli Arbel; Karen Yorav; Rolf Drechsler
Complete and Effective Robustness Checking by Means of Interpolation. In: Formal Methods in Computer-Aided Design 2012. Formal Methods in Computer-Aided Design (FMCAD-2012), October 22-25, Cambridge, England, United Kingdom, o.A. 2012.
- Rolf Drechsler; Melanie Diepenbeck; Daniel Große; Ulrich Kühne; Hoang M. Le; Julia Seiter; Mathias Soeken; Robert Wille
Completeness-Driven Development. In: G. Rozenberg; H.-J. Kreowski; G. Engels; H. Ehrig (Hrsg.). Proceedings of the 6th International Conference on Graph Transformation 2012 "Modeling and Analysis of Dynamic Structures". International Conference on Graph Transformation (ICGT-2012), 6th, - Modeling and Analysis of Dynamic Structures -, September 24-29, Bremen, Germany, Lecture Notes in Computer Science (LNCS), Vol. 7562, Springer, 2012.
- Finn Haedicke; Hoang M. Le; Daniel Große; Rolf Drechsler
CRAVE: An Advanced Constrained RAndom Verification Environment for SystemC. In: Proceedings of the International Symposium on System-on-Chip 2012. International Symposium on System-on-Chip (SoC-2012), October 11-12, Tampere, Finland, IEEE, 2012.
- Marc Michael; Daniel Große; Rolf Drechsler
Localizing Features of ESL Models for Design Understanding. In: Proceedings of the Forum on Specification & Design Languages 2012. Forum on Specification & Design Languages (FDL-2012), September 18-20, Vienna, Austria, IEEE, 2012.
- Rolf Drechsler; Mathias Soeken; Robert Wille
Formal Specification Level: Towards Verification-driven Design Based on Natural Language Processing. In: Proceedings of the Forum on Specification & Design Languages 2012. Forum on Specification & Design Languages (FDL-2012), September 18-20, Vienna, Austria, IEEE, 2012.
- Robert Wille; Mathias Soeken; Eleonora Schönborn; Rolf Drechsler
Circuit Line Minimization in the HDL-based Synthesis of Reversible Logic. In: Proceedings of the IEEE Computer Society Annual Symposium on VLSI 2012. IEEE Computer Society Annual Symposium on VLSI (ISVLSI-2012), August 19-21, Amherst, Masachusetts, United States, IEEE, 2012.
- Melanie Diepenbeck; Mathias Soeken; Daniel Große; Rolf Drechsler
Behavior Driven Development for Circuit Design and Verification. In: Proceedings of the IEEE International Workshop on High-Level Design Validation and Test 2012. IEEE International Workshop on High-Level Design Validation and Test (HLDVT-2012), November 9-10, Huntington Beach, CA, United States, IEEE, 2012.
- Kamalika Datta; Indranil Sen Gupta; Hafizur Rahaman; Rolf Drechsler
An Evolutionary Approach to Reversible Logic Synthesis using Output Permutation. In: IEEE Design and Test Symposium . IEEE Design and Test Symposium (IEEE IDT-12), December 15-17, Doha, Qatar, IEEE, 2012.
2011
- Stephan Eggersglüß; Rolf Drechsler
As-Robust-As-Possible Test Generation in the Presence of Small Delay Defects using Pseudo-Boolean Optimization. In: Proceedings of the GI/GMM/ITG Workshop Testmethoden und Zuverlässigkeit von Schaltungen und Systemen. GI/GMM/ITG Workshop Testmethoden und Zuverlässigkeit von Schaltungen und Systemen (TuZ-11), February 27 - March 1, Passau, Germany, o.A. 2011.
- Stephan Eggersglüß; Rolf Drechsler
As-Robust-As-Possible Test Generation in the Presence of Small Delay Defects using Pseudo-Boolean Optimization. In: Proceedings of DATE 11 - Design, Automation & Test in Europe. The European Event for Electronic System Design & Test. Design, Automation & Test in Europe (DATE-11), March 14-18, Grenoble, France, o.A. 2011.
- Stephan Eggersglüß; Rolf Drechsler
Efficient Data Structures and Methodologies for SAT-based ATPG providing High Fault Coverage in Industrial Application. In: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), Vol. 30, No. 9, Pages 1411-1415, IEEE Press, 2011.
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