Identification of Efficient Clustering Techniques for Test Power Activity on the Layout

Harshad Dhotre, Stephan Eggersglüß, Rolf Drechsler

In: 26th IEEE Asian Test Symposium (ATS). Asian Test Symposium (ATS-26) November 27-30 Taipei Taiwan 2017.


With the increase in transistor density in state-of-the-art circuits the power behavior of integrated circuits changesdrastically, which may result in device failures. This may becomeworse while testing, because of the high transient activity insmaller area. This may lead to high power consumption andfailures in certain areas as compared to other parts of the die.For this reason, high power density areas on the integratedcircuits need to be identified on the layout to avoid effectssuch as IR-drop, EM and noise as early as possible. Previously,this was usually considered by manually dividing the layout inequal blocks. However, this method may not provide the desiredaccuracy due to e.g. boundary effects and manual errors. Inthis paper, we propose the use of pattern recognition/machinelearning techniques to dynamically partition the layout in clustersto identify high power density areas under test application.We show how machine learning techniques can be used tomodel the clustering problem and analyze the feasibility aswell as the performance of several algorithms on benchmarkcircuits. These techniques avoid the errors on static boundariesand account for pattern dependent behavior. Furthermore, theproposed clustering is validated by comparing the results to acontour of an industrial tool.

German Research Center for Artificial Intelligence
Deutsches Forschungszentrum für Künstliche Intelligenz