Approximation-aware Testing for Approximate Circuits

Arun Chandrasekharan, Stephan Eggersglüß, Daniel Große, Rolf Drechsler

In: 23rd Asia and South Pacific Design Automation Conference (ASP-DAC). Asia and South Pacific Design Automation Conference (ASP-DAC-23) 23rd January 22-25 Jeju South Korea 2018.


A wide range of applications significantly benefitfrom the Approximate Computing (AC) paradigm in terms ofspeed or power reduction. AC achieves this by tolerating errorsin the design. These errors are introduced into the designeither manually by the designer or by approximate synthesisapproaches. From here, the standard design flow is taken. Hence,the manufactured AC chip is eventually tested for productionerrors using well established fault models. To be precise, if thetest for a test pattern fails, the AC chip is sorted out. However,from a general perspective this procedure results in throwingaway chips which are perfectly fine taking into account that theconsidered fault (i.e. physical defect that leads to the error) canstill be tolerated because of approximation. This can lead to asignificant amount of yield loss.In this paper, we present an approximation-aware test meth-odology which can be easily integrated into the regular test flow.It is based on a pre-process to identify approximation-redundantfaults. By this, we remove all potential faults that no longerneed to be tested because they can be tolerated under the givenerror metric. Our experimental results and case studies on awide variety of benchmark circuits show a significant potentialfor yield improvement.


German Research Center for Artificial Intelligence
Deutsches Forschungszentrum für Künstliche Intelligenz