Fast and Accurate Performance Evaluation for RISC-V using Virtual Prototypes

Vladimir Herdt, Daniel Große, Rolf Drechsler

In: Design, Automation and Test in Europe (DATE). Design, Automation & Test in Europe (DATE-2020) March 9-13 Grenoble France 2020.


RISC-V is gaining huge popularity in particular forembedded systems. Recently, a SystemC-basedVirtual Prototype(VP) has been open sourced to lay the foundation for providingsupport for system-level use cases such as design space exploration,analysis of complex HW/SW interactions and power/timing/perfor-mance validation for RISC-V based systems.In this paper, we propose an efficient core timing model and in-tegrate it into the VP core to enable fast and accurate performanceevaluation for RISC-V based systems. As a case-study we providea timing configuration matching the RISC-V HiFive1 board fromSiFive. Our experiments demonstrate that our approach allowsto obtain very accurate performance evaluation results while stillretaining a high simulation performance.


Deutsches Forschungszentrum für Künstliche Intelligenz
German Research Center for Artificial Intelligence