Efficient Techniques to Strongly Enhance the Virtual Prototype based Design Flow

Vladimir Herdt, Rolf Drechsler

In: IEEE Computer Society Annual Symposium on VLSI (ISVLSI). IEEE Computer Society Annual Symposium on VLSI (ISVLSI-2020) July 6-8 Limassol Cyprus 2020.


SystemC-based Virtual Prototypes (VPs) are an industry-proven solution to tackle the rising complexity of em-bedded systems in the design flow. This paper proposes a comprehensive set of novel approaches that strongly enhance all major aspects of a modern VP-based design flow. A strong emphasis is puton automated formal verification methods and advanced coverage-guided testing techniques tailored for SystemC-based VPs and alsothe software. In addition, we consider VP modeling techniquesthat cover functional as well as non-functional aspects and also propose automated correspondence analyses between the hardware- and VP-level to utilize information available at different levels ofabstraction. All approaches have been extensively evaluated withseveral experiments that clearly demonstrate their effectivenessin strongly enhancing the VP-based design flow, in particularby drastically improving the overall quality in combination with a reduction in time-to-market. Furthermore, this paper puts aparticular focus on the modern RISC-VInstruction Set Architecture (ISA).


Deutsches Forschungszentrum für Künstliche Intelligenz
German Research Center for Artificial Intelligence