Publikationen

In: Design, Automation and Test in Europe Conference (DATE 2023). Design, Automation & Test in Europe (DATE-2023), April 17-19, Antwerp, Belgium, 2023.

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In: IEEE Internet of Things Journal (IoT), Vol. o.a. IEEE, 2023.

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In: 28th IEEE European Test Symposium 2023. IEEE European Test Symposium (ETS-2023), May 22-26, Venice, Italy, 2023.

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In: 28th IEEE European Test Symposium 2023. IEEE European Test Symposium (ETS-2023), May 22-26, Venice, Italy, 2023.

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In: International Symposium on Quality Electronic Design (ISQED'23). International Symposium on Quality Electronic Design (ISQED-2023), April 5-7, San Francisco, CA, USA, 2023.

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In: International Symposium on Quality Electronic Design (ISQED'23). International Symposium on Quality Electronic Design (ISQED-2023), April 5-7, San Francisco, CA, USA, 2023.

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In: 35. GI/GMM/ITG Testmethoden und Zuverlässigkeit von Schaltungen und Systemen (TuZ). GI/GMM/ITG Workshop Testmethoden und Zuverlässigkeit von Schaltungen und Systemen (TuZ-2023), February 26-28, Erfurt, Germany, 2023.

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In: IEEE Transactions on Circuits and Systems II: Express Briefs, IEEE, 2023.

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In: 5th Workshop on Parallel AI and Systems for the Edge (PAISE). Workshop on Parallel AI and Systems for the Edge (PAISE-2023), located at IPDPS 2023, April 19 - May 19, St. Petersburg, FL, USA, 2023.

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In: Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV). ITG/GMM/GI-Workshop "Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen" (MBMV-2023), March 23-24, Freiburg, Germany, 2023.

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Publikationen

Design Enablement Flow for Circuits with Inherent Obfuscation based on Reconfigurable Transistors

Specification-based Symbolic Execution for Stateful Network Protocol Implementations in the IoT

Synthesis of IJTAG Networks for Multi-Power Domain Systems on Chips

Increasing SAT-Resilience of Logic Locking Mechanisms using Formal Methods

VAST: Validation of VP-based Heterogeneous Systems against Availability Security Properties using Static Information Flow Tracking

Polynomial Formal Verification of a Processor: A RISC-V Case Study

New Directions for Equivalence Checking of System-Level and SPICE-Level Models of Linear Circuits

MARADIV: Library of MAGIC based Approximate Restoring Array Divider Benchmark Circuits for In-Memory Computing Using Memristors

Fast and Accurate: Machine Learning Techniques for Performance Estimation of CNNs for GPGPUs

Security Validation of VP-based Heterogeneous Systems: A Completeness-driven Perspective

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