Publikationen

In: Proceedings of the 28th Asia and South Pacific Design Automation Conference (ASP-DAC). Asia and South Pacific Design Automation Conference (ASP-DAC-2023), February 16-19, Tokyo, Japan, 2023.

Zur Publikation

In: Proceedings of the 28th Asia and South Pacific Design Automation Conference (ASP-DAC). Asia and South Pacific Design Automation Conference (ASP-DAC), January 16-19, Tokyo, Japan, 2023.

Zur Publikation

In: Design, Automation and Test in Europe Conference (DATE). Design, Automation & Test in Europe (DATE-2023), April 17-19, Antwerp, Belgium, 2023.

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In: Design, Automation and Test in Europe Conference (DATE). Design, Automation & Test in Europe (DATE-2023), April 17-19, Antwerp, Belgium, 2023.

Zur Publikation

In: Design, Automation and Test in Europe (DATE). Design, Automation & Test in Europe (DATE-2023), April 17-19, Antwerp, Belgium, 2023.

Zur Publikation

In: Design, Automation and Test in Europe (DATE). Design, Automation & Test in Europe (DATE-2023), April 17-19, Antwerp, Belgium, 2023.

Zur Publikation

In: Design, Automation and Test in Europe (DATE). Design, Automation & Test in Europe (DATE-2023), April 17-19, Antwerp, Belgium, 2023.

Zur Publikation

In: Proceedings of the 28th Asia and South Pacific Design Automation Conference (ASP-DAC). Asia and South Pacific Design Automation Conference (ASP-DAC-2023), January 16-19, Tokyo, Japan, 2023.

Zur Publikation

In: 15th International Conference on Agents and Artificial Intelligence (ICAART). International Conference on Agents and Artificial Intelligence (ICAART-2023), February 22-24, Lissabon, Portugal, 2023.

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In: 35. GI/GMM/ITG Testmethoden und Zuverlässigkeit von Schaltungen und Systemen (TuZ). GI/GMM/ITG Workshop Testmethoden und Zuverlässigkeit von Schaltungen und Systemen (TuZ-2023), February 26-28, Erfurt, Germany, 2023.

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Publikationen

Automated Equivalence Checking Method for Majority based In-Memory Computing on ReRAM Crossbars

EDDY: A Multi-Core BDD Package With Dynamic Memory Management and Reduced Fragmentation

Polynomial Formal Verification of Floating Point Adders

Processor Verification using Symbolic Execution: A RISC-V Case-Study

Equivalence Checking of System-Level and SPICE-Level Models of Static Nonlinear Circuits

FELOPi: A Framework for Simulation and Evaluation of Post-Layout File Against Optical Probing

Extending the Design Space of Dynamic Quantum Circuits for Toffoli based Network

Trojan-D2: Post-Layout Design and Detection of Stealthy Hardware Trojans - a RISC-V Case Study

Coverage-guided Fuzzing for Plan-based Robotics

Remote Configuration Methodology for IEEE 1687 Scan Networks

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