Publikation

Constraint-based Pattern Retargeting for Reducing Localized Power Activity during Testing

Harshad Dhotre, Stephan Eggersglüß, Rolf Drechsler, Mehdi Dehbashi, Ulrike Pfannkuchen

In: 21st IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS). IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS-21) April 25-27 Budapest Hungary 2018.

Abstrakt

Highly compact as well as compressed test patterngeneration may result in the aggregation of high power activityin specific areas on a manufactured circuit during testing. Thesehotspots can lead to electromigration and IR-drop in local blocksof the chip resulting in wrong test results. This is due to thecircumstance that the effect of localized high switching activity isnot precisely taken into consideration during ATPG and patternsimulation. Discarding such patterns may result in test coverageloss. Low power test generation methods typically reduce theswitching activity globally across the pattern and not locally inspecific areas. Additionally, these methods typically increase thetest data volume as well as the testing time. In this paper, a testpattern retargeting methodology is proposed which takes pattern-specific, dynamically identified hotspots into account. Criticalpatterns and their corresponding critical regions are identified.Based on this data, constraints are used for pattern retargetingpreventing the previously identified local hotspots. In contrast toprevious methods, the proposed retargeting technique ensures ahigh test coverage without a large pattern inflation.

Deutsches Forschungszentrum für Künstliche Intelligenz
German Research Center for Artificial Intelligence