Synchronization and channel decoding are integral parts of each receiver in wireless communication systems. The task of synchronization is the estimation of the general unknown parameters of phase, frequency, and timing offset as well as correction of the received symbol sequence according to the estimated parameters.
There are three types of synchronization: Data-Aided (DA), Non-Data-Aided (NDA), and Code-Aided (CA). DA or NDA synchronization is performed once prior to channel decoding. Additionally, CA is performed after each iteration of Turbo decoder to improve the synchronization quality.
This thesis focuses on hardware implementation of code-aided synchronization (CAS). To support multiple wireless communication standards, flexibility is required. This required flexibility is provided with an ASIP implementation. The designed ASIP has been synthesised on a Xilinx Virtex 6 FPGA and 65nm CMOS standard library. The ASIP is validated using validation tools such as Processor Debugger and ModelSIM and the concept is proven.