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Logic Synthesis for Hybrid CMOS-ReRAM Sequential Circuits

Saman Fröhlich; Saeideh Shirinzadeh; Rolf Drechsler
In: IEEE Computer Society Annual Symposium on VLSI (ISVLSI) 2019. IEEE Computer Society Annual Symposium on VLSI (ISVLSI-2019), July 15-17, Miami, Florida, USA, 2019.


Resistive Random Access Memory (ReRAM) is anemerging non-volatile technology with high scalability and zerostandby power which allows to perform logic primitives. ReRAMcrossbar arrays combined with a CMOS substrate provide a widerange of benefits in logic synthesis.In this paper, we propose to exploit ReRAM in sequentialcircuits as it provides both required features as a computationaland memory element. We propose a fully automated synthesisapproach based on graph representations (i.e., BDDs and AIGs)for synthesis of sequential circuits on hybrid CMOS-ReRAMarchitectures. We propose an algorithm to efficiently divide thetarget function into two independent computational parts. Thisallows to merge part of the computation within a ReRAM unitand utilize its computational capabilities besides its function asa sequential element in order to minimize the CMOS overhead.Experimental results show that ReRAM allows for a significantreduction in CMOS size of up to 40.9% for BDDs with an averageof 8.7% for BDDs and up to 10.1% with an average of 3.2% forAIGs.I