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ASCHyRO: Automatic Fault Localization of SystemC HLS Designs Using a Hybrid Accurate Rank Ordering Techniqu

Mehran Goli; Alireza Mahzoon; Rolf Drechsler
In: 38th IEEE International Conference on Computer Design (ICCD). IEEE International Conference on Computer Design (ICCD-2020), October 18-21, Hartford, USA, 2020.


In order to meet time-to-market constraints andto raise the design productivity, High-level Synthesis(HLS) is being increasingly adopted by the semiconductor industry. HLS designs, which can be automatically translated into RegisterTransfer Level(RTL), are typically written in SystemC at the Electronic System Level (ESL). However, this modern design flow still has weaknesses, in particular, due to the significant manual effort involved for verification and the subsequent debugging process which are both time-consuming and error-prone. In this paper, we propose ASCHyRO, a fully automated semi-formal fault localization approach for SystemC HLS designs. ASCHyRO takes advantage of a hybrid rank ordering technique to derive a reduced ordered set of potential fault locations. The reduced order set is obtained by calculating a Confidence Score(CS) for each fault candidate based on a combination of staticand dynamic fault probability analysis. Experimental results including an extensive set of standard SystemC HLS designs show the effectiveness of our approach in localizing even multiple faults with high confidence in a short execution time.