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LAT-UP: Exposing Layout-Level Analog Hardware Trojans Using Contactless Optical Probing

Sajjad Parvin; Mehran Goli; Thilo Krachenfels; Shahin Tajik; Jean-Pierre Seifert; Frank Sill Torres; Rolf Drechsler
In: IEEE Computer Society Annual Symposium on VLSI. IEEE Computer Society Annual Symposium on VLSI (ISVLSI-2023), June 20-23, Iguazu Falls, Brazil, 2023.


The insertion of a Hardware Trojan (HT) into a chip after the in-house layout design is outsourced to a chip manufacturer for fabrication is a major concern, especially for mission-critical applications. While several HT detection methods have been developed based on side-channel analysis and physical measurements to overcome this problem, there exist stealthy analog HTs, i.e., capacitive and dopant-level HTs, which have negligible or even zero overhead on the chip. Thus, these stealthy HTs cannot be detected using the aforementioned methods. In this work, we propose a novel analytical approach to detect these Layout-level Analog Trojans (LAT). Our proposed method uses an extension of Optical Probing (OP) for LAT detection, namely, the Laser Logic State Imaging (LLSI) technique. In principle, to detect LATs using LLSI, we only need the golden design and not a golden chip, which is not typically available. As we take advantage of LLSI to detect HTs, our approach is non-invasive, less costly, and scalable to larger designs. We report experimental results on a malicious RISC-V to demonstrate the effectiveness of our approach in detecting LATs.