Project | ECXL

The goal of the ECXL project is to develop a design and verification platform for RISC-V based systems. The verification platform will allow models on the abstract electronic system level as well as on the concrete register transfer level in a consistent way. This cross-level modeling combines the advantages of both levels: while the electronic system level allows early software development and design space exploration with virtual prototypes, the lower register transfer level models can be efficiently synthesized. In addition, the design platform is intended to support the extension of the RISC-V ISA with application-specific instructions at both modeling levels. The consistency between the two levels is demonstrated by the consistency of both with the RISC-V-ISA. The ECXL verification platform will be validated with two case studies from the field of self-verification and edge AI.