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Towards ML-based Performance Estimation of Embedded Software: A RISC-V Case Study

Weiyan Zhang; Muhammad Hassan; Rolf Drechsler
In: Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV). ITG/GMM/GI-Workshop "Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen" (MBMV-2024), February 14-15, Landau, Germany, 2024.


Performance estimation of embedded software techniques mimic the behavior of real hardware, consistently navigating a balance between simulation accuracy and speed. Designers usually use real hardware, simulators, or static analyzers to obtain the performance. However, these methods suffer from serious drawbacks as real hardware is not available in the early stage of the design process, simulators either do not support any timing accuracy or require large execution time, and static analyzers need details of the hardware microarchitecture. Recently, Machine Learning (ML) has been successfully applied to estimate performance, in particular the clock cycles. It can significantly facilitate the exploration of a wide range of microarchitecture solutions at the early stage, applicable across various architectures. In this paper, we delve into the advancements of ML-based performance estimation on RISC-V processors, leveraging performance statistics obtained directly from a fast functional simulator using built-in counters. The proposed approach uses dynamic analysis for feature extraction and different ML algorithms including regression algorithms and Neural Network (NN) for the generation of Predictive Models (PMs). We present a comprehensive analysis of their effectiveness across diverse RISC-V implementations.