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Cross-Level Verification of Hardware Peripherals

Sallar Ahmadi-Pour; Muhammad Hassan; Rolf Drechsler
In: RISC-V Summit Europe. RISC-V Summit Europe, June 24-28, München, Germany, 2024.


In this extended abstract we present a Virtual Prototype (VP) driven verification methodology for Hardware (HW) peripherals. Our verification methodology is twofold: A Coverage-Guided Fuzzing (CGF) based approach enables comprehensive verification at the unit-level, while an application-driven co-simulation approach enables verification at the system level. As a case-study, we utilize a RISC-V Platform Level Interrupt Controller (PLIC) as HW peripheral and use an abstract Transaction Level Modeling (TLM) PLIC implementation from the open source RISC-V VP as the reference model. In our experiments, we find three behavioral mismatches as well as non-functional timing behavior mismatches. As the different approaches uncover different types of mismatches, we conclude a synergy between the methods to aid in verification efforts.