Publication
A New SAT-based ATPG for Generating Highly Compacted Test Sets
Stephan Eggersglüß; Rene Krenz-Baath; Andreas Glowatz; Friedrich Hapke; Rolf Drechsler
In: Proceedings. IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS-12), 15th, April 18-20, Tallinn, Estonia, IEEE, 2012.
Abstract
The test set size is a highly important factor in the
post-production test of circuits. A high pattern count in the test
set leads to long test application time and exorbitant test costs.
We propose a new test generation approach which has the ability
to reduce the test set size significantly. In contrast to previous
SAT-based ATPG techniques which were focused on dealing with
hard single faults, the proposed approach employs the robustness
of SAT-solvers to primarily push test compaction. Furthermore,
a concept is introduced how the novel technique can be flexibly
integrated into an existing industrial flow to reduce the pattern
count. Experimental results on large industrial circuits show that
the approach is able to reduce the pattern count of up to 63%
compared to state-of-the-art dynamic compaction techniques.