Cognitive Assistants

Page 57 of 58.

1. Rolf Drechsler; Mathias Soeken; Robert Wille

   Formal Specification Level: Towards Verification-driven Design Based on Natural Language Processing

   In: Proceedings of the Forum on Specification & Design Languages 2012. Forum on Specification & Design Languages (FDL-2012), September 18-20, Vienna, …

2. Melanie Diepenbeck; Mathias Soeken; Daniel Große; Rolf Drechsler

   Behavior Driven Development for Circuit Design and Verification

   In: Proceedings of the IEEE International Workshop on High-Level Design Validation and Test 2012. IEEE International Workshop on High-Level Design …

3. Kamalika Datta; Indranil Sen Gupta; Hafizur Rahaman; Rolf Drechsler

   An Evolutionary Approach to Reversible Logic Synthesis using Output Permutation

   In: Proceedings of IEEE International Design and Test Symposium . IEEE International Design and Test Symposium (IDT-12), December 15-17, Doha, Qatar, …

4. Mathias Soeken; Robert Wille; Christoph Hilken; Nils Przigoda; Rolf Drechsler

   Synthesis of Reversible Circuits with Minimal Lines for Large Functions

   In: Conference Proceedings. Asia and South Pacific Design Automation Conference (ASP-DAC-12), 17th, January 30 - February 2, Sydney, New South Wales, …

5. Robert Wille; Mathias Soeken; Rolf Drechsler

   Debugging of Inconsistent UML/OCL Models

   In: Conference Proceedings. Design, Automation & Test in Europe (DATE-12), March 12-16, Dresden, Germany, 2012.

6. Mathias Soeken; Robert Wille; Rolf Drechsler

   Eliminating Invariants in UML/OCL Models

   In: Conference Proceedings. Design, Automation & Test in Europe (DATE-12), March 12-16, Dresden, Germany, 2012.

7. Robert Wille; Rolf Drechsler; Christof Oswald; Alberto Garcia-Ortiz

   Automatic Design of Low-Power Encoders Using Reversible Circuit Synthesis

   In: Conference Proceedings Design, Automation & Test in Europe. Design, Automation & Test in Europe (DATE-12), March 12-16, Dresden, Germany, 2012.

8. Robert Wille; Mathias Soeken; Eleonora Schönborn; Rolf Drechsler

   Circuit Line Minimization in the HDL-based Synthesis of Reversible Logic

   In: Proceedings of the IEEE Computer Society Annual Symposium on VLSI 2012. IEEE Computer Society Annual Symposium on VLSI (ISVLSI-2012), August …

9. Stephan Eggersglüß; Melanie Diepenbeck; Robert Wille; Rolf Drechsler

   Towards Increasing Test Compaction Abilities of SAT-based ATPG through Fault Detection Constraints

   In: Proceedings. IEEE Workshop on RTL and High Level Testing (WRTLT-12), IEEE, 2012.

10. Stephan Eggersglüß; Rolf Drechsler

    As-Robust-As-Possible Test Generation in the Presence of Small Delay Defects using Pseudo-Boolean Optimization

    In: Proceedings of the GI/GMM/ITG Workshop Testmethoden und Zuverlässigkeit von Schaltungen und Systemen. GI/GMM/ITG Workshop Testmethoden und …

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