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Endurance Management for ResistiveLogic-In-Memory Computing Architectures

Saeideh Shirinzadeh; Mathias Soeken; Pierre-Emmanuel Gaillardon; Giovanni De Micheli; Rolf Drechsler
In: Design, Automation and Test in Europe (DATE). Design, Automation & Test in Europe (DATE-2017), March 27-31, Lausanne, Switzerland, 2017.


Resistive Random Access Memory(RRAM) is apromising non-volatile memory technology which enables mod-ern in-memory computing architectures. Although RRAMs areknown to be superior to conventional memories in many aspects,they suffer from a low write endurance. In this paper, we focus onbalancing memory write traffic as a solution to extend the lifetimeof resistive crossbar architectures. As a case study, we monitorthe write traffic in aProgrammable Logic-in-Memory(PLiM)architecture, and propose an endurance management schemefor it. The proposed endurance-aware compilation is capableof handling different trade-offs between write balance, latency,and area of the resulting PLiM implementations. Experimentalevaluations on a set of benchmarks including large arithmetic andcontrol functions show that the standard deviation of writes canbe reduced by 86.65% on average compared to a naive compiler,while the average number of instructions and RRAM devices alsodecreases by 36.45% and 13.67%, respectively.