Machine Learning-based Prediction of Test Power

Harshad Dhotre; Stephan Eggersglüß; Krishnendu Chakrabarty; Rolf Drechsler

In: 24th IEEE European Test Symposium (ETS 19). IEEE European Test Symposium (ETS-2019), May 27-31, Baden Baden, Germany, 2019.


With the increase in circuit complexity, the gapbetween circuit development time and analysis time has widened.A large database is required in order to perform essential analysistasks such as power, thermal, and IR-drop analysis, which, inturn, leads to long run times. This work focuses on test poweranalysis. Due to the large number of test patterns for moderndesigns and the excessive power analysis run time for eachtest, it is not feasible to obtain complete power profiles forall the tests. However, test power-safety is essential to producereliable manufacturing test results and prevent yield loss andchip damage. Accurate power profiling can typically be donefor a small subset of pre-selected tests only. An essential taskis therefore to determine those tests, which potentially providethe worst-case scenarios with respect to test power. We proposemachine learning-based power prediction for test selection. Theprediction is applied in two different ways. First, we predict theactivity of a test to identify tests with high power consumption.Second, the switching activity and the power information arerelated to the layout of the chip to identify local hot spots.Various machine learning-based algorithms are used to evaluatethis approach. Additionally, the algorithms are compared againsteach other. The results indicate high prediction accuracy andeffectiveness. This makes these algorithms well suited for worst-case test selection.

Deutsches Forschungszentrum für Künstliche Intelligenz
German Research Center for Artificial Intelligence