Automated Analysis of Virtual Prototypes at Electronic System Level

Mehran Goli; Muhammad Hassan; Daniel Große; Rolf Drechsler

In: 29th ACM Great Lakes Symposium on VLSI (GLSVLSI). ACM Great Lakes Symposium on VLSI (GLSVLSI-2019), May 9-11, Washington, DC, USA, 2019.


The exponential increase in functionality ofSystem-on-Chips(SoCs)and reducedTime-to-Market(TTM) requirements have significantlyaltered the typical design and verification flow.Virtual Prototyp-ing(VP) at theElectronic System Level(ESL) using SystemC anditsTransaction Level Modeling(TLM) framework is an industry-accepted solution. VP design exploration, review, debugging, andintegration of ever changing functional requirements can be madefaster with the help of design understanding and visualization meth-ods. Hence, in this paper, we propose a fully automated structural,and behavioral analysis approach for visualization of ESL VPs in-cluding TLM-2.0 VPs. At the heart of the analysis is a hybrid ap-proach which uses static and dynamic methods to extract structuraland behavioral information of the VP. Afterwards, the extractedinformation is translated into structural and graphical represen-tations such as UML diagrams (specifying TLM-2.0 transactions’protocols), and XML format (describing designs’ structure). Experi-mental results including a real-world VP shows the effectiveness ofour approach.


Deutsches Forschungszentrum für Künstliche Intelligenz
German Research Center for Artificial Intelligence