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New Directions for Equivalence Checking of System-Level and SPICE-Level Models of Linear Circuits

Kemal Çağlar Coşkun; Muhammad Hassan; Rolf Drechsler
In: 35. GI/GMM/ITG Testmethoden und Zuverlässigkeit von Schaltungen und Systemen (TuZ). GI/GMM/ITG Workshop Testmethoden und Zuverlässigkeit von Schaltungen und Systemen (TuZ-2023), February 26-28, Erfurt, Germany, 2023.


In this paper, we present a novel, graph-based methodology to formally check equivalence between system-level and SPICE-level representations of Single-Input Single-Output (SISO) linear analog circuits. To achieve this, we introduce a canonical representation in the form of a Signal-Flow Graph (SFG), which is used to functionally map the system-level and SPICE-level models. We create SFG representations for SPICElevel models and system-level models, and use graph manipulation techniques to transform the SFG representations into the canonical representation. We demonstrate the applicability of the methodology by successfully applying it to complex circuits.