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Investigating Various Adder Architectures for Digital In-Memory Computing Using MAGIC-based Memristor Design Style

Chandan Jha; Alireza Mahzoon; Rolf Drechsler
In: 6th International Conference on Emerging Electronics (ICEE). IEEE International Conference on Engineering and Emerging Technologies (ICEET), December 11-14, Bangalore, India, 2022.


Adders are implemented using a wide variety of architectures. These architectures have been extensively studied for digital IC-based implementations. In recent years, in-memory computing has gained interest owing to the benefits it provides in terms of both energy and performance as compared to conventional von Neumann computing. In this work, we for the first time investigate various adder architectures for in-memory computing using the memristor aided logic (MAGIC) design style for memristors. We analyze seven different adder architectures for bit-widths: 8-bit, 16-bit, 32-bit, and 64-bit. We have used the state-of-the-art SIMPLER tool for performing the mapping of these adders to memristor crossbars. We show that serial prefix adders are better suitable for IMC using the MAGIC design style as compared to the widely used ripple carry adder. The adder designs and the mapping will be made open source at, to promote further research in the direction.