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Automatic Mapping of the Sum-Product Network Inference Problem to FPGA-Based Accelerators

Lukas Sommer; Julian Oppermann; Alejandro Molina; Carsten Binnig; Kristian Kersting; Andreas Koch
In: 36th IEEE International Conference on Computer Design. IEEE International Conference on Computer Design (ICCD-2018), October 7-10, Orlando, FL, USA, Pages 350-357, IEEE Computer Society, 2018.


In recent years, FPGAs have been successfully employed for the implementation of efficient, application-specific accelerators for a wide range of machine learning tasks. In this work, we consider probabilistic models, namely, (Mixed) Sum-Product Networks (SPN), a deep architecture that can provide tractable inference for multivariate distributions over mixed data-sources. We develop a fully pipelined FPGA accelerator architecture, including a pipelined interface to external memory, for the inference in (mixed) SPNs. To meet the precision constraints of SPNs, all computations are conducted using double-precision floating point arithmetic. Starting from an input description, the custom FPGA-accelerator is synthesized fully automatically by our tool flow. To the best of our knowledge, this work is the first approach to offload the SPN inference problem to FPGA-based accelerators. Our evaluation shows that the SPN inference problem benefits from offloading to our pipelined FPGA accelerator architecture.

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