A Highly Fault-Efficient SAT-Based ATPG Flow

Stephan Eggersglüß; Rolf Drechsler

In: IEEE Design & Test of Computers, Vol. 29, No. 4, Pages 63-70, IEEE Press, 7/2012.


ATPG algorithms have to provide a high fault coverage in order to satisfy the quality demands of the chip industry. However, classical structural ATPG algorithms have problems to cope with the increased complexity of modern designs. The number of unclassified faults grows and the demands of the industry are compromised. ATPG based on Boolean Satisfiability (SAT) is a promising alternative to structural algorithms being very robust. This article proposes a novel SAT-based ATPG flow, which allows for the efficient application in industrial practice. A SAT instance generation flow is proposed enabling the efficient generation of high-quality tests. Additionally, new ATPG-specific SAT solving techniques are presented which boost the performance and robustness of SAT-based ATPG. Experimental results on large industrial circuits with multi-million elements show a significantly increased fault efficiency and very high fault coverage. This makes SAT-based ATPG suitable for the complexity of future designs and new complex fault models.

Deutsches Forschungszentrum für Künstliche Intelligenz
German Research Center for Artificial Intelligence