Hybrid Architecture for Embedded Test Compression to Process Rejected Test Patterns

Sebastian Huhn, Daniel Tille, Rolf Drechsler

In: 24th IEEE European Test Symposium (ETS). IEEE European Test Symposium (ETS-2019) May 27-31 Baden Baden Germany 2019.


This work presents a novel hybrid compressionarchitecture that seamlessly combines the advantages of an em-bedded test compression technique with a lightweight codeword-based compression scheme. The proposed architecture tacklesthe shortcomings of state-of-the-art techniques, which are widelyto address the rising challenges of safety-critical applicationsenforcing a zero defect policy. Embedded test compression tech-niques had been introduced that allow the compression of alarge share of the test patterns. However, depending on the testapplication (e.g. low pin count test) there is a certain number oftest patterns, which are incompressible due to the architectureand will be rejected. This leads to a test coverage decrease which,in turn, jeopardizes the zero defect policy. Therefore, the rejectedtest patterns are typically transferred in an uncompressed waybypassing the embedded compression, which is extremely costly.The proposed hybrid architecture mitigates the adverse impactof rejected test patterns on the compression ratio as well ason the test application time of state-of-the-art techniques. Theexperimental evaluation of industrial-sized designs clearly showsthat a significant compression ratio up to 67.4% and a testapplication time reduction up to 65.7% can be achieved.

2019_ETS_HybridEDT.pdf (pdf, 793 KB )

Deutsches Forschungszentrum für Künstliche Intelligenz
German Research Center for Artificial Intelligence