SAT-Hard: A Learning-based Hardware SAT-Solver

Buse Ustaoglu, Sebastian Huhn, Frank Sill Torres, Daniel Große, Rolf Drechsler

In: EUROMICRO Digital System Design Conference (DSD). Euromicro Conference on Digital System Design (DSD-2019) August 28-30 Kallithea, Chalkidiki Greece 2019.


Within the last decades, tremendous research work has been carried out on the development of software-based algorithms to solve the Boolean Satisfiability Problem. These SAT-solvers have then been heavily orchestrated for addressing complex computational tasks like the verification of circuits. In this field, most of the applied techniques focused only on the design phase of the circuit. Due to this fact, new approaches have been published in the literature solely focusing on online verification as well as self-verification. These kind of solutions strictly require Hardware (HW) SAT-solvers that can be integrated into a system while introducing only low hardware overhead and still providing high flexibility. By following these observations, this work presents SAT-Hard: In contrast to the state-of-theart, SAT-Hard takes advantage of learning techniques to support features like clause learning and non-chronological backtracking, and combines them within a lightweight and standalone HW device. By this, a run-time speed-up of 2,000x can be achieved. Furthermore, the experimental evaluation clearly demonstrates that those complex problems can be solved in less than 20 seconds. Particularly due to its compactness, SAT-Hard is suitable for self-verification that enables the continuous verification of an integrated system during its lifetime.


Deutsches Forschungszentrum für Künstliche Intelligenz
German Research Center for Artificial Intelligence