Efficient Cross-Level Testing for Processor Verification: A RISC-V Case-Study

Vladimir Herdt, Daniel Große, Eyck Jentzsch, Rolf Drechsler

In: Forum on Specification & Design Languages (FDL). Forum on Specification & Design Languages (FDL-2020) September 15-17 Kiel Germany 2020.


Extensive processor verification at the Register-Transfer Level(RTL) is crucial to avoid bugs. Therefore, simulation-based approaches are prevalent but they require efficient test generation methods to achieve a thorough verification.In this paper we propose an efficient cross-level testing approach for processor verification targeting the RISC-VInstruction Set Architecture(ISA). We generate an endless instruction stream without restrictions on the generated instructions by evolving the instruction stream on-the-fly during simulation. An Instruction Set Simulator(ISS) is leveraged as reference model for the RTL core under test in a tightly coupled cross-level co-simulation setting. This enables a very efficient and comprehensive testing process. As a case-study we present results on the verification of the 32 bit pipelined RISC-V core of MINRESThe Good Folk (TGF) SeriesOur approach has beenvery effective in finding several serious bugs.


Deutsches Forschungszentrum für Künstliche Intelligenz
German Research Center for Artificial Intelligence