System Level verification of Phase-Locked Loop using Metamorphic Relations

Muhammad Hassan, Daniel Große, Rolf Drechsler

In: Design, Automation and Test in Europe Conference (DATE). Design, Automation & Test in Europe (DATE-2021) February 1-5 virtual 2021.


System-on-Chips(SoC) have imposed new yet stringent design specifications on the Radio Frequency(RF) subsystems. The Timed DataFlow(TDF) model of computation available in SystemC-AMS offers here a good trade-off between accuracy and simulation-speed at the system-level. However, one of the main challenges in system-level verification is the availability of reference models traditionally used to verify the correctness of the Design Under Verification (DUV). Recently, Metamorphic testing(MT) introduced a new verification perspective in the software domain to alleviate this problem. MTun covers bugs just by using and relating test-cases.In this paper, we present a novel MT-based verification approach to verify the linear and non-linear behaviors of RF amplifiers at the system-level. The central element of our MT-approach is a set of Metamorphic Relations(MRs) which describes the relation of the inputs and outputs of consecutive DUV executions. For the class of Low Noise Amplifiers (LNAs) we identify12high-quality MRs. We demonstrate the effectiveness of our proposed MT-based verification approach in an extensive set of experiments on an industrial system-level LNA model without the need of a reference model.


Deutsches Forschungszentrum für Künstliche Intelligenz
German Research Center for Artificial Intelligence