Fast Logic Synthesis for RRAM-based In-Memory Computing using Majority-Inverter Graphs

Saeideh Shirinzadeh, Mathias Soeken, Pierre-Emmanuel Gaillardon, Rolf Drechsler

In: Design, Automation and Test in Europe (DATE). Design, Automation & Test in Europe (DATE) March 14-18 Dresden Germany 2016.


Resistive Random Access Memories(RRAMs) havegained high attention for a variety of promising applicationsespecially the design of non-volatile in-memory computing devices.In this paper, we present an approach for the synthesis ofRRAM-based logic circuits using the recently proposedMajority-Inverter Graphs(MIGs). We propose a bi-objective algorithmto optimize MIGs with respect to the number of requiredRRAMs and computational steps in both MAJ-based and IMP-based realizations. Since the number of computational steps isrecognized as the main drawback of the RRAM-based logic,we also present an effective algorithm to reduce the numberof required steps. Experimental results show that the proposedalgorithms achieve higher efficiency compared to the generalpurpose MIG optimization algorithms, either in finding a goodtrade-off between both cost metrics or reducing the number ofsteps. In comparison with the RRAM-based circuits implementedby the state-of-the-art approaches using other well-known datastructures the number of required computational steps obtainedby our proposed MIG-oriented synthesis approach for largebenchmark circuits is reduced up to factor of 26. This stronggain comes from the use of MIGs that provide an efficient and in-trinsic representation for RRAM-based computing—particularlyin MAJ-based realizations—and the use of techniques proposedfor optimization.

Deutsches Forschungszentrum für Künstliche Intelligenz
German Research Center for Artificial Intelligence