Publikation

Machine Learning Based Test Pattern Analysis for Localizing Critical Power Activity Areas

Harshad Dhotre, Stephan Eggersglüß, Mehdi Dehbashi, Ulrike Pfannkuchen, Rolf Drechsler

In: 30th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT). IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT-2017) October 23-25 Cambridge United Kingdom 2017.

Abstrakt

The identification of power-risky test patterns is acrucial task in the design phase of digital circuits. Excessivetest power could lead to test failures due to IR-drop, noise,etc. This has to be avoided to prevent yield loss and chipdamages. However, the accurate power simulation of all testpatterns to identify power-risky patterns as well as to findcritical areas within each pattern is not possible due to runtime and resource constraints. An important task is thereforethe selection of a subset of potentially power-risky patterns,which will be simulated in an accurate manner. In this paper,we propose an independent test pattern analysis methodologyfor the integration into an existing industrial design flow. Theproposed test pattern analysis technique is a lightweight methodbased on the cell’s Transient Power Activity (TPA) to identifypotentially power-risky patterns. The method uses layout andpower information to identify critical power activity areas usingmachine learning techniques. Experiments were performed onopensource benchmarks as well as on an industrial design. Theresults were correlated with commercial power and IR-dropsimulation tools. The proposed methodology was found to beeffective in terms of speed and localization of the critical areasfor unsafe patterns.

Deutsches Forschungszentrum für Künstliche Intelligenz
German Research Center for Artificial Intelligence