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Cyber-Physical Systems

Publikationen

Seite 3 von 114.

Moritz Schmidt; Abhoy Kole; Leon Wichette; Rolf Drechsler; Frank Kirchner; Elie Mounzer
Exploration of Design Alternatives for Reducing Idle Time in Shor's Algorithm: A Study on Monolithic and Distributed Quantum Systems
In: ArXiv e-prints (arxiv), Vol. abs/2503.22564, Arxiv, 2025.
Saeideh Nabipour; Kamalika Datta; Lennart Weingarten; Abhoy Kole; Rolf Drechsler
Multi-Input MAGIC Synthesis and Verification for In-Memory Computing Design
In: IEEE International Symposium on Multiple-Valued Logic (ISMVL). IEEE International Symposium on Multiple-Valued Logic (ISMVL-2025), June 5-6, Montreal, Canada, 2025.
Weiyan Zhang; Muhammad Hassan; Rolf Drechsler
LLM-assisted Performance Estimation of Embedded Software on RISC-V Processors
In: 28th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS). IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS-2025), May 5-7, Lyon, France, 2025.
Karl Aaron Rudkowski; Sallar Ahmadi-Pour; Rolf Drechsler
CrosSym: Cross-Level Verification of SystemC Peripherals using Symbolic Execution
In: 28th International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS). IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS), May 5-7, 2025.
Till Schnittka; Chandan Jha; Sallar Ahmadi-Pour; Rolf Drechsler
RIVER: Sneak Path Aware READ-based In-Memory Computing for 1T1M Memristive Crossbars
In: 28th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS). IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS-2025), May 5-7, Lyon, France, 2025.
Kemal Çağlar Coşkun; Chandan Jha; Muhammad Hassan; Rolf Drechsler
Formal Verification of Error Bounds for Resistive-Switching-based Multilevel Matrix-Vector Multipliers
In: 26th International Symposium on Quality Electronic Design (ISQED'25). International Symposium on Quality Electronic Design (ISQED-2025), April 23-25, San Francisco, USA, 2025.
Jan Zielasko; Rolf Drechsler
Optimizing Hardware for Neural Network Inference using Virtual Prototypes
In: RISC-V Summit Europe. RISC-V Summit Europe, May 12-15, Paris, France, 2025.
Spandan Das; Christoph Lüth; Rolf Drechsler
Designing Memory Protection for a RISC-V Nano-VP
In: Proceedings of the 3rd Workshop on Nano Security: From Nano-Electronics to Secure Systems (NanoSec'25). Workshop on Nano Security: From Nano-Electronics to Secure Systems (NanoSec-25), March 29 - April 2, Lyon, France, 2025.
Lennart Weingarten; Kamalika Datta; Sallar Ahmadi-Pour; Abhoy Kole; Rolf Drechsler
Ensuring Correctness Efficiently for RISC-V Processors with Customised Multiplier Designs
In: Design and Verification of Cyber-Physical Systems: From Theory to Applications, Science Direct, 2025.
Bernhard J. Berger; Christina Plump; Rolf Drechsler
Why less is sometimes more: Using Boolean literals to solve 2048
In: IT - information technology (IT), Vol. 66, Pages 4-5, De Gruyter Brill, 2025.