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RISC-V Opt-VP: An Application Analysis Platform Using Bounded Execution Trees

Jan Zielasko; Rune Krauss; Marcel Merten; Rolf Drechsler
In: RISC-V Summit Europe. RISC-V Summit Europe, June 24-28, München, Germany, 2024.


Tailoring hardware to applications significantly increases their performance, which is required to meet the rising demand for resource-limited devices in the area of embedded systems. While RISC-V facilitates applicationspecific solutions due to its extensibility, Virtual Prototypes (VPs) enable early software development before the actual hardware is built shortening the time-to-market. Although the RISC-V VP ecosystem already offers many useful tools to aid development there is still room for improvement, especially in analyzing applications for hardware optimization. To address the aforementioned issue and expand the mentioned ecosystem with a tool, this work presents RISC-V Opt-VP, which generates bounded execution trees in order to analyze applications. An embedded application analysis case study illustrates that promising instruction sequences are found which can also be merged to further improve their execution coverage, enabling efficient hardware designs.