Publikationen

Seite 3 von 3.

Stephan Eggersglüß; Kenneth Schmitz; Rene Krenz-Baath; Rolf Drechsler
Using Optimization Techniques to Increase Test Compaction
In: IEEE Workshop on RTL and High Level Testing - Proceedings. IEEE Workshop on RTL and High Level Testing (WRTLT-13), 14th, November 21-22, Jiaosi, …
Stephan Eggersglüß; Rolf Drechsler
A Highly Fault-Efficient SAT-Based ATPG Flow
In: IEEE Design & Test of Computers, Vol. 29, No. 4, Pages 63-70, IEEE Press, 7/2012.
Stephan Eggersglüß; Rolf Drechsler
High Quality Test Pattern Generation and Boolean Satisfiability
ISBN 978-1-4419-9975-7, Springer, 3/2012.
Stephan Eggersglüß; Rene Krenz-Baath; Andreas Glowatz; Friedrich Hapke; Rolf Drechsler
A New SAT-based ATPG for Generating Highly Compacted Test Sets
In: Proceedings. IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS-12), 15th, April 18-20, Tallinn, Estonia, IEEE, …
Stephan Eggersglüß; Mahmut Yilmaz; Krishnendu Chakrabarty
Robust Timing-Aware Test Generation Using Pseudo-Boolean Optimization
In: Proceedings. Asian Test Symposium (ATS-12), 21st, November 19-22, Niigata, Japan, IEEE-Verlag, 2012.
Stephan Eggersglüß; Melanie Diepenbeck; Robert Wille; Rolf Drechsler
Towards Increasing Test Compaction Abilities of SAT-based ATPG through Fault Detection Constraints
In: Proceedings. IEEE Workshop on RTL and High Level Testing (WRTLT-12), IEEE, 2012.
Stephan Eggersglüß; Rolf Drechsler
As-Robust-As-Possible Test Generation in the Presence of Small Delay Defects using Pseudo-Boolean Optimization
In: Proceedings of the GI/GMM/ITG Workshop Testmethoden und Zuverlässigkeit von Schaltungen und Systemen. GI/GMM/ITG Workshop Testmethoden und …
Stephan Eggersglüß; Rolf Drechsler
As-Robust-As-Possible Test Generation in the Presence of Small Delay Defects using Pseudo-Boolean Optimization
In: Proceedings of DATE 11 - Design, Automation & Test in Europe. The European Event for Electronic System Design & Test. Design, Automation & Test in …
Stephan Eggersglüß; Rolf Drechsler
Efficient Data Structures and Methodologies for SAT-based ATPG providing High Fault Coverage in Industrial Application
In: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), Vol. 30, No. 9, Pages 1411-1415, IEEE Press, 2011.